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| Ordering number : EN*5422 CMOS LSI LC82220 Motion JPEG Decoder LSI Preliminaly Overview The LC82220 is a single-chip JPEG decoder designed for wide range of digital video playback applications including amusement systems, video games and PC JPEG playback cards. The LC82220 is capable of decoding JPEG bitstreams of SIF resolution with a picture rate of 30 frames/sec. The digital video output can be formatted for NTSC, PAL, SECAM, or any other optional video standard. The complete decoding function is realised with the LC82220, a standard 8-bit or 16-bit microcontroller and a bank of DRAM. A typical memory configuration is a single 128 k x 16 or 256 k x 16 DRAM. The LC82220 also supports efficient video display functions such as scroll and overlay. Package Dimensions unit: mm 3182-QFP128E [LC82220] Functions * * * * * * * * * * * * * Support for JPEG format Real-time decoding of motion-JPEG with rate of 30 frames/sec Lowest solution cost for amusement, game, PC systems Support for YUV 4:1:1 color format YUV or RGB digital video outputs compatible with optional video format Programmable picture and display window format Support for trick display: scrolling, overlaying Standard 8/16-bit microcontroller interface with DMA support for compressed data input Support SOI and EOI markers Direct connect to video DAC Direct connect to 2 M or 4 M DRAM as bit and frame buffers Two Q-tables included High-speed processing by fixed Huffman tables SANYO: QIP128E SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 62096HA (OT) No. 5422-1/6 LC82220 Block Diagram Pin Assignment No. 5422-2/6 LC82220 Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Symbol VDD ZCTLINT ZCTLCS ZCTLRD ZCTLWR ZCTLRDY TEST3 TEST4 CTLA5 CTLA4 CTLA3 CTLA2 CTLA1 CTLA0 CTLCPU VDD VSS CTLD7 CTLD6 CTLD5 CTLD4 CTLD3 CTLD2 CTLD1 CTLD0 TEST0 ZRESET CLKSEL0 CLKSEL1 CLK TEST1 VDD VSS ZCDCS/ZCDACK ZCDINT/ZCDREQ ZCDWR ZCDRDY CCD15 CCD14 CCD13 CCD12 CCD11 CCD10 CCD9 CCD8 CCD7 CCD6 VSS VDD CCD5 CCD4 CCD3 CCD2 CCD1 CCD0 I I I I I I Code bus data I O I O I I I I I I I I I I Ground +5 V power supply Code bus data I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I Test pin Hardware reset Clock divisor setting CLKSEL1:0 = 00: no divisor, 01: clock divided by 2, 10: clock divided by 3 System (decode) clock input (CMOS level input) Test pin +5 V power supply Ground Code bus select or Code bus DMA acknowledge Code bus interrupt or Code bus DMA request Code bus data write signal Code bus ready (tristate output) Control bus data O I I I O I I I I I I I I I Control bus CPU type selection +5 V power supply Ground Control bus address I/O +5 V power supply Control bus interrupt request (open drain output) Control bus select Control bus read or R/W select Control bus write or Data strobe Control bus ready (tristate output) Test pin Test pin Function Continued on next page. No. 5422-3/6 LC82220 Continued from preceding page. Pin No. 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 Symbol DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VSS VDD ZBLANK ZPXEN PXCLK ZVSYNC ZHSYNC DG7 DG6 DG5 DG4 DG3 DG2 DG1 DG0 TEST2 VDD VSS DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 VSS ZOE ZWEL ZRAS ZCASL ZWEH/ZCASH VDD VSS MD15 MD14 MD13 MD12 MD11 MD10 VDD VSS MD9 MD8 MD7 MD6 MD5 MD4 I/O I/O I/O I/O I/O I/O Frame memory interface data bus I/O I/O I/O I/O I/O I/O +5 V power supply Ground Frame memory interface data bus O O O O O O O O O O O O O Ground Memory output enable Memory write enable (L) Row address strobe Column address strobe (L) Memory write enable (H)/column address strobe (H) +5 V power supply*1 Ground Pixel data bus R (Y) O I I I I O O O O O O O O I Test pin +5 V power supply Ground Pixel data bus G (U) I/O O O O O O O O O Ground +5V power supply Blanking signal Pixel data enable signal Pixel clock Vertical synchronizing signal Horizontal synchronizing signal Pixel data bus B (V) Function Continued on next page. No. 5422-4/6 LC82220 Continued from preceding page. Pin No. 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Symbol VSS VDD MD3 MD2 MD1 MD0 VSS MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 VSS O O O O O O O O O Ground Frame memory address signals I/O I/O I/O I/O Ground Frame memory interface data bus I/O Ground +5 V power supply Function System Configuration Example 1. Separate code bus type This is a system in which the code and system busses are separated. The coded data input does not load down the system bus. No. 5422-5/6 LC82220 2. Shared code bus type This is a system in which code bus and the system bus are connected. Coded data is written by the CPU, or alternatively, data can be written using the DMA controller. s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice. No. 5422-6/6 |
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